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programmable monolithic 4 chan- nel codec/filter single +3.3v supply pin strap / mcu control mode a/ m law programmable linear coding (16 bits) option pcm highway format automatically detected: 1.536 or 1.544mhz; 2.048, 4.096, 8192 mhz tx gain programming: 16db range; <0.1db step rx gain programming: 26db range; <0.1db step programmable time slot assign- ment digital and analog loopbacks slic control port static mode (16 i/os) dynamic mode (12 i/os + 4 cs) 64 tqfp package pcm in hi-z mode description the STLC5046 is a monolithic programmable 4 channel codec and filter. it operates with a single +3.3v supply. the analog interface is based on a receive output buffer driving the slic rx input and on an amplifier input stage. due to the single supply voltage a proper midsupply reference level is generated internally by the device and all ana- log signals are referred to this level (agnd). the pcm interface uses one common 8khz frame sync. pulse for transmit and receive direction. the bit clock can be selected between four standards: 1.536/1.544mhz, 2.048mhz, 4.096mhz, 8192mhz. device programmability is achieved by means of 41 registers allowing to set the dif- ferent parameters like tx/rx gains, encoding law (a/ m ), time slot assignment, independent chan- nels power up/down, loopbacks, pcm bits offset. thanks to pinstrap option, the most significant of the above parameters can be set by hardware connection of dedicated pins. this allow to use this device also on line card without mcu on board. when pin strap option is selected different pins of the device will change their function (see pin description). in mcu control mode the STLC5046 can be pro- grammed via serial interface running up to 4mhz. one interrupt output pin is also provided. this is preliminary information on a new product now in development. details are subject to change without notice. december 1999 ? tqfp64 ordering number: STLC5046 STLC5046 programmable four channel codec and filter product preview 1/27
absolute maximum ratings symbol parameter value unit v cc v cc to v ee -0.5 to 4.6 v v dd v dd to v ss -0.5 to 4.6 v v di digital input input pin voltage -0.5 to 5.5 v i out output pin current 1ma t stg storage temperature range -65 to +150 c t lead lead temperature (soldering, 10s) 300 c v ai analog pin input voltage -0.5 to 4.6 v operating range symbol parameter value unit v cc ,v dd supply voltage 3.3 5% v t op operating temperature range -40 to +85 c thermal data symbol parameter value unit r th j-amb thermal resistance junction-ambient 70 c/w gr0 gr0 gr0 gr0 d/a sigma-delta decimators tx filters rx filters interpolators arbiter encoder decoder programmable gain rx programmable gain tx vfro0 vfro1 vfro2 vfro3 vfxi0 vfxi1 vfxi2 vfxi3 fs/fs0 mclk tsx dx dr slic control registers 8bit 8bit 17-bit bus data contlol to analog fe post filter post post post filter filter filter programmable functions 8-bit bus a/d a/d a/d a/d anti-alias anti-alias anti-alias anti-alias gx0 gx1 gx2 gx3 a/u law a/u law pcm interface & slot assgn digital processor analog frontend vee vcc pll interface control serial cs / pd1 co / gr0 ci / pd0 cclk / gr1 int / amu cs0 / gx0 cs1 / gx1 cs2 / gx2 cs3 / gx3 io0 / gr2 io1 / pd2 io2 / gr3 io3 / pd3 io7 io8 io9 io10 io11 cap vdd vss sub config. port io4 / fs1 io5 / fs2 io6 / fs3 m0 m1 block diagram gr0 gr1 gr2 gr3 STLC5046 2/27
analog n. name type function 33 vfro0 ao receive analog amplifier output channel 0. pcm data received on the programmed time slot on dr input is decoded and appears at this output. 39 vfro1 ao receive analog amplifier output channel 1. pcm data received on the programmed time slot on dr input is decoded and appears at this output. 42 vfro2 ao receive analog amplifier output channel 2. pcm data received on the programmed time slot on dr input is decoded and appears at this output. 48 vfro3 ao receive analog amplifier output channel 3. pcm data received on the programmed time slot on dr input is decoded and appears at this output. 1 2 3 5 6 4 7 8 9 10 27 11 28 29 30 31 32 59 58 57 56 54 55 53 52 51 50 49 43 42 41 39 38 40 48 47 46 44 45 ci/pd0 co/gr0 cs/pd1 res res int/amu dx dr vdd cclk/gr1 vss io3/pd3 io4/fs1 io5/fs2 vcc5 m0 vee5 cs0/gx0 cs1/gx1 vee1 vee0 n.c. io9 io10 io11 vcc4 m1 vee4 cs2/gx2 cs3/gx3 vee2 vee3 n.c. vfxi2 vfro2 sub vfro1 vfxi1 cap vfro3 n.c. vfxi3 vcc2 vcc3 d98tl405 22 23 24 25 26 60 io8 61 io7 62 io6/fs3 63 res 64 n.c. n.c. n.c. io0/gr2 io1/pd2 io2/gr3 17 18 19 20 21 37 36 34 33 35 vcc1 vcc0 n.c. vfro0 vfxi0 12 13 14 15 16 n.c. n.c. fs/fs0 tsx mclk pin connection (top view) pin description i/o definition type definition ai analog input ao analog output odo open drain output di digital input do digital output dio digital input/output dto digital tristate output dps digital power supply aps analog power supply STLC5046 3/27
n. name type function 35 vfxi0 ai tx input amplifier channel 0. typ 1m w input impedance 38 vfxi1 ai tx input amplifier channel 1. typ 1m w input impedance 43 vfxi2 ai tx input amplifier channel 2. typ 1m w input impedance 46 vfxi3 ai tx input amplifier channel 3. typ 1m w input impedance 40 cap ai agnd voltage filter pin. a 100nf capacitor must be connected between ground and this pin. power supply 25, 36, 37, 44, 45, 56, vcc/0/1/2/3/ 4/5 aps total 6 pins: 3.3v analog power supplies, should be shorted together, require 100nf decoupling capacitor to vee. 26,30, 31, 50, 51,55 vee/0/1/2/3/ 4/5 aps total 6 pins: analog ground, should be shorted together. 9 vdd dps digital power supply 3.3v, require 100nf decoupling capacitor to vss. 8 vss dps digital ground 41 sub dps substrate connection. must be shorted together with vee and vss pins as close as possible the chip. not connected 15, 16, 17, 18, 32, 34, 47, 49, 64 n.c. not connected. 1,2,63 res reserved: must be left not connected. digital 27 m0 di mode select, see m1 m1 m0 mode select 0 1 pin-strap mode: basic functions selected by proper pin strapping 1 0 mcu mode: device controlled via serial interface 0 0 reset status 1 1 not allowed 54 m1 di 13 mclk di master clock input. four possible frequencies can be used: 1.536/1.544 mhz; 2.048 mhz; 4.096 mhz; 8.192 mhz. the device automatically detect the frequency applied. this signal is also used as bit clock and it is used to shift data into and out of the dr and dx pins. 12 tsx odo transmit time slot (open drain output, 3.2ma). normally it is floating in high impedance state except when a time slot is active on the dx output. in this case tsx output pulls low to enable the backplane line driver. 11 dx dto transmit pcm interface. it remains in high impedance state except during the assigned time slots during wich the pcm data byte is shifted out on the rising edge of mclk. 10 dr di receive pcm interface. it remains inactive except during the assigned receive time slots during which the pcm data byte is shifted in on the falling edge of mclk. 61 io7 dio slic control i/o pin #7. can be programmed as input or output via dir register. depending on content of conf register can be a static input/output or a dynamic input/output synchronized with the csn output signals controlling the slics. pin description (continued) analog STLC5046 4/27
n. name type function 60 io8 dio slic control i/o pin #8. (see io7 description). 59 io9 dio slic control i/o pin #9. (see io7 description). 58 io10 dio slic control i/o pin #10. (see io7 description). 57 io11 dio slic control i/o pin #11. (see io7 description). digital (dual mode) 14 fs/fs0 di mcu control mode: fs. frame sync. pulse. a pulse or a squarewave waveform with an 8khz repetition rate is applied to this pin to define the start of the receive and transmit frame. effective start of the frame can be then shifted of up to 7 clock pulses indipendently in receive and transmit directions by proper programming of the pcmsh register. pin-strap control mode: fs0. frame sync. pulse of channel #0. one mclk cycle long , starts pcm data transfer in the time slot following its falling edge (short frame delayed timing). 19 io0/gr2 dio/di mcu control mode: io0. slic control i/o pin #0. can be programmed as input or output via dir register. depending on content of conf register can be a static input/output or a dynamic input/output synchronized with the csn output signals controlling the slics. pin-strap control mode: gr2. receive gain programming channel 2: 1: receive gain = = -0.8db 0: rec. gain = -4.3db 20 io1/pd2 dio/di mcu control mode: io1. slic control i/o pin #1. (see io0 description). pin-strap control mode: pd2. power down command channel 2: 1: channel 2 codec is in power down. (equivalent to conf reg bit2 = 1) 0: channel 2 codec is in power up. (equivalent to conf reg. bit2 = 0) 21 io2/gr3 dio/di mcu control mode: io2. slic control i/o pin #2. (see io0 description) pin-strap control mode: gr3. receive gain programming channel 3. (see gr2 description) 22 io3/pd3 dio/di mcu control mode: io3. slic control i/o pin #3. (see io0 description). pin-strap control mode: pd3. power down command channel 3. (see pd2 description) 23 io4/fs1 dio/di mcu control mode: io4 slic control i/o pin #4. (see io0 description). pin-strap control mode: fs1. frame sync. pulse of channel #1. one mclk cycle long , starts pcm data transfer in the time slot following its falling edge (short frame delayed timing). 24 io5/fs2 dio/di mcu control mode: io4. slic control i/o pin #5. (see io0 description). pin-strap control mode: fs2. frame sync. pulse of channel #1. one mclk cycle long , starts pcm data transfer in the time slot following its falling edge (short frame delayed timing). 62 io6/fs3 dio/di mcu control mode: io4. slic control i/o pin #6. (see io0 description). pin-strap control mode: fs3. frame sync. pulse of channel #1. one mclk cycle long , starts pcm data transfer in the time slot following its falling edge (short frame delayed timing). pin description (continued) digital STLC5046 5/27
n. name type function 28 cs0/gx0 do/di mcu control mode: cs0. slic cs control #0. depending on conf reg. content can be a cs output for slic #0 or a static i/o. when configured as cs output it is automatically generated by the codec with a repetition time of 31.25 m s. in this mode also the io 11..0 are synchronized and carry proper data in and out synchronous with cs. pin-strap control mode: gx0. transmit gain programming channel 0: 1: transmit gain = 0db 0: transmit gain = - 3.5db 29 cs1/gx1 do/di mcu control mode: cs1: slic cs control #1, (see cs0 description). pin-strap control mode: gx1. transmit gain programming channel 1 (see gx0 description) 53 cs2/gx2 do/di mcu control mode: cs2. slic cs control #2, (see cs0 description). pin-strap control mode: gx2. transmit gain programming channel 2 (see gx0 description) 52 cs3/gx3 do/di mcu control mode: cs3. slic cs control #3, (see cs0 description). pin-strap control mode: gx3. transmit gain programming channel 3 (see gx0 description) 4 cs/pd1 di/di mcu control mode: cs. chip select of serial control bus. when this pin is low control information can be written to or read from the device via the ci and co pins. pin-strap control mode: pd1. power down command channel 1. (see pd2 description). 7 cclk/gr1 di/di mcu control mode: cclk. clock of serial control bus. this clock shifts serial control ilnformation into or out of ci or co when cs input is low depending on the current instruction. cclk may be asyncronous with the other system clocks. pin-strap control mode: gr1. receive gain programming ch. 1, (see gr2 description). 6 ci/pd0 di/di mcu control mode: ci. control data input of serial control bus. control data is shifted in the device when cs is low and clocked by cclk. pin-strap control mode: pd0. power down command channel 0. (see pd2 description). 5 co/gr0 dto/di mcu control mode: co. control data output of serial control bus. control data is shifted out the device when cs is low and clocked by cclk. during the first 8 cclk pulses the co pin is h. i., valid data are shifted out during the following 8 cclk pulses. pin-strap control mode: gr0. receive gain programming ch. 0, (see gr2 description). 3 int/amu odo/di mcu control mode: int. interrupt output (open drain), goes low when a data change has been detected in the i/o pins. one mask registers allow to mask any i/o pin. interrupt is reset when the i/o register is read. pin-strap control mode: amu. a/ m law selection: amu=0: m law amu=1: a law, even bit inverted pin description (continued) STLC5046 6/27
functional description power on initialization when power is first applied it is recommended to reset the device by forcing the condition m1.0=00, in order to to clear all the internal regis- ters. in mcu mode m0 is set steadily low and the de- vice is reset by applying a negative pulse to m1 (its operative level in mcu mode is high); same result can be obtained by writing an high level into the control bit res of the conf register. in pin-strap mode m1 is set steadily low and the device is reset by applying a negative pulse to m0 (its operative level in pin-strap mode is high); at the end of the reset phase (m0=high) the de- vice is programmed according to the logical con- figuration of the control pins. during the reset condition all the i/on and cs_n pins are set as inputs , dx is set in high imped- ance and all vfron outputsare forced to agnd. power down state each of the four channel may be put into power down mode by setting the appropriate bit in the conf register or strapping to vdd the proper pin. in this mode the eventual programmed dx channel is set in high impedance while the vfro outputs are forced to agnd. in pin strap mode the value forced on the input pin is internally up- dated every fs signal. transmit path the analog vfxi signal through an amplifier stage is applied to a pcm converter and the cor- responding digital signal is sent to dx output. in mcu mode, the amplifier gain can be pro- grammed with two different values by means of txg reg. : 0db or +3.52 db. a programmable gain block after the a/d conver- sion allows to set transmit gain in 12db range, with steps <0.1db by writing proper code into gtxn register. setting gtxn=00h , the transmitted signal is muted, i.e. an idle pcm signal is generated on dx. a/ m coding law is selected by bit5 (amu) of conf reg. setting lin=1 (bit6 of conf reg.) the linear cod- ing law is selected (16bits); in this case the sig- nal sent on dx will take two adjacent pcm time slots. in pin-strap mode, the amplifier gain is set to 0db; only two values of transmit gain can be se- lected according to the level of gxn control input (in pin-strap): gxn=1 selects the gain corresponding to gtxn=ffh (0db) gxn=0 selects the gain corresponding to gtxn=8fh ( -3.5db) different gain value is obtained through proper voltage divider. a/ m coding law is selected according to amu pin level: amu=0 m -law selected. amu=1 a-law selected. vfxi input must be ac coupled to the signal source; the voltage swing allowed is 1.0vpp vfro a/ m dr gr 8 bit linear 1/4 to 1 sd conv. rxg: 0db -1.94d b -4.44d b -7.96d b -13. 98db for rxg=0db; gr=0db (ff) 0dbm0 => -3dbm| 600 w figure 2. receive path. vfxi txg: 0db +3.52db 1m w sd conv. gx a/ m 8 bit linear 1/4 to 1 agnd for txg=0db; gx=0db (ff) -15dbm| 600 w 0dbm0 dx figure 1. transmit path. STLC5046 7/27
when the preamplifier gain is set 0db or 0.66vpp if the gain is set to 3.52db (mcu mode only); higher levels must be reduced through proper di- viders. typical impedance of vfxi input is 1mohm. receive path the received pcm signal dr through the de- coder section, the gain select block and the d/a converter is converted in an analog signal which is transfered to vfro output through an ampli- fier stage. in mcu mode a programmable gain block before the a/d conversion allows to set receive gain in 12db range, with steps <0.1db by writing proper code into grxn register. the amplifier gain can be programmed with five different values by means of rxg register: 0db -1.94db -4.44db -7.96db -13.98db. setting grxn=00h , the receive signal is muted and vfro output is set to agnd. a/ m coding law is selected by bit5 (amu) of conf reg. setting lin = 1 (bit6 of conf reg.) the linear coding law is selected (16bits); in this case the signal received on dr will take two adjacent pcm time slots. in pin strap mode only two values of receive gain can be selected according to the level of grn control input (in pin strap) grn = 1 selects the gain corresponding to grxn = e2h, rxg = 0db (-0.8db) grn = 0 selects the gain corresponding to grxn = afh, rxg = -1.94db (-4.3db) different gain value is obtained through proper voltage divider. a/ m coding law is selected according to amu pin level: amu=0 m -law selected. amu=1 a-law selected. vfro output, referred to agnd must be ac coupled to the load, referred to vss, to prevent a dc current flow. vfro has a drive capability of 1.0ma (peak value), with a max ac swing of 2vpp. in order to get the best noise performances it is recommended to keep the grx value as close as possible to the maximum (ffh) setting properly the additional attenuation by means of rxg. pcm interface the STLC5046 dedicate five pins (six in pin strap mode) to the interface with the pcm highways. mclk represents the bit clock and is also used by the device as a source for the clock of the in- ternal sigma delta converter timings. four possi- ble frequencies can be used: 1.536/1.544mhz (24 channels pcm frame); 2048mhz (32 chan- nels pcm frame); 4.096mhz (64 channels pcm frame); 8.192mhz (128 channels pcm frame). the operating frequency is automatically de- tected by the device when both mclk and fs are applied. mclk is synchronizing both the transmit data (dx) and the receive data (dr). mcu mode: the frame sync. signal fs is the common time base for all the four channels; short (one mclk period) or long (more than one mclk period) fs are allowed. transmit and receive programmable time-slots are framed to an internal sync. signal that can be coincident with fs or delayed of 1 to 7 mclk cy- cles depending on the programming of pcmsh d7..................d0 d7...................d0 fs fs receive time slot transmit time slot dxan reg. dran reg. ts0 ts23/31/61/12 7 figure 3. mcu mode: time - slot assignment STLC5046 8/27
register. dx represent the transmit pcm interface. it re- mains in high impedance state except during the assigned time slots during which the pcm data byte is shifted out on the rising edge of mclk. the four channels can be shifted out in any pos- sible timeslot as defined by the dxa0 to dxa3 registers. if one codec is set in power down by software programming the corresponding timeslot is set in high impedance. when linear coding mode is selected by conf register programming the output channel will need two consecutive timeslots (see register description). dr represent the receive pcm interface. it re- mains inactive except during the assigned time slots during wich the pcm data byte is shifted in on the falling edge of mclk. the four channels are shifted in any possible timeslot as defined by the dra0 to dra3 registers. pin strap mode when pinstrap mode is selected, dedicated frame sync. fs3..0 are provided on dual func- tion pins: mcu pin-strap pin fs fs0 12 io4 fs1 17 io5 fs2 18 io6 fs3 48 the pcmsh register cannot be accessed, there- fore the beginning of the transmit and receive frame is identified by the rising edge of the fsn signal. each channel has its dedicated frame sync. sig- nal fsn. short or long frame timing is automat- ically selected; depending on the fs signal ap- plied to fs0 input. the assigned time slot (transmit and receive) takes place in the 8 mclk cycles following the falling edge of fsn in case of short frame or the rising edge in case of long frame. if one codec is set in power down by proper pin strap configuration the correspond- ing timeslot is not loaded and the vfro output is kept at steady agnd level. finally by means of the loopb register is possi- ble to implement a digital or analog loopback on any of the selected channels. tsx represent the transmit time slot (open drain output, 3.2ma). normally it is floating in high impedance state except when a time slot is active on the dx output. in this case tsx output pulls low to enable the backplane line driver. should be strapped to vss when not used. control interface STLC5046 has two control modes, a microproc- essor control mode and a pin strap control mode. the two modes are selected by m0 and m1 pins. when m0 = low, m1 = high (mcu control mode) the mcu port is activated; and the 41 registers of the device can be programmed. when m0 = high, m1 = low (pin-strap mode) the microprocessor control port is disabled and some of the digital pins change their function allowing to perform a very basic programming of the device. d7..................d0 d7...................d0 receive /transmit time slot ts23/31/61/127 d7...................d0 fs0 fsn fsm ch0 chn chm figure 4. pin strap mode: time slot assignment table 1. control byte structure. first byte (address) 76543210 r/w d/s a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 r/w = 0: write register r/w = 1: read register d/s = 0: single byte d/s = 1: two bytes a5..a0: register address STLC5046 9/27
in pin-strap mode the status of the control pins is entered at power-on reset and refreshed at any frame sync. cycle. in mcu mode the control information is written to or read from STLC5046 via the serial four wires control bus : cclk : control clock cs : chip select input ci : serial data input co : serial data output all control instructions require 2 bytes, with the ex- ception of the single byte for command synchroni- zation. the first byte specify the register address, and the type of access (read or write). the second byte contain the data to be loaded into the register (on ci wire) or carried out the register content (on co wire) depending on the r/w bit of the first byte. co wire is normally in high imped- ance and goes to low impedance only during the second byte in case of read operation. this allows to use a common wire for both ci/co. serial data ci is shifted to the serial input register on the rising edge of cclk and co is shifted out on the falling. cs, normally high, is set low during the trans- mission / reception of a byte, lasting 8cclk pulses . though, in general, two bytes of the same in- struction take two cs separated cycles , STLC5046 can handle the data transfer in a sin- gle 16 cclk cs cycle, in both the directions. one additional wire provided to the control inter- face is an open drain interrupt output (int) that goes low when a change of status is detected on the i/o pins. slic control interface the device provides 12 i/o pins plus 4 cs signals. the interface can work in dynamic or static mode: it can be selected by means of dir register. dynamic mode: the i/o pins are configured as input or output by means of dir register. the cs signals are used to select the different slic interface. in this case the i/o pin can be multi- plexed. the data loaded from slic#n via i/o pins configured as input can be read in the datan register. the data written in a datan register will be loaded on the i/o pins configured as output when the csn signal will be active. static mode: the cs signal can be used as i/o pins. they can be configured as input or out- put i/o by means of data1 register. the data corresponding to the cs signal can be read or written by means of data2 register. all data related to th other i/o pins can be read or writ- ten by means of data0 register. registers addresses (only mcu mode) addr. name description 00h conf configuration register 01h dir-l i/o direction (bit 7-0) 02h dir-h i/o direction (bit 11-8) 03h data0-l i/o data ch#0/ static data; (bit 7-0) 04h data0-h i/o data ch#0/ static data ; (bit 11-8) 05h data1-l i/o data ch#1 (bit 7-0) / cs direction 06h data1-h i/o data ch#1 (bit 11-8) 07h data2-l i/o data ch#1 (bit 7-0) / cs data 08h data2-h i/o data ch#2 (bit 11-8) 09h data3-l i/o data ch#3 (bit 7-0) 0ah data3-h i/o data ch#3 (bit 11-8) 0bh gtx0 transmit gain ch#0 0ch gtx1 transmit gain ch#1 0dh gtx2 transmit gain ch#2 0eh gtx3 transmit gain ch#3 0fh grx0 receive gain ch#0 10h grx1 receive gain ch#1 11h grx2 receive gain ch#2 12h grx3 receive gain ch#3 13h dxa0 transmit timeslot ch#0 14h dxa1 transmit timeslot ch#1 15h dxa2 transmit timeslot ch#2 16h dxa3 transmit timeslot ch#3 17h dra0 receive timeslot ch#0 18h dra1 receive timeslot ch#1 19h dra2 receive timeslot ch#2 1ah dra3 receive timeslot ch#3 1bh pcmsh pcm shift register 1ch dmask-l interrupt mask i/o port (03h) 1dh dmask-h interrupt mask i/o port (04h) 1eh cmask interrupt mask i/o port (07h) 1fh pchk-a persistency check time for input a 20h pchk-b persistency check time for input b 21h int interrupt register 22h alarm alarm register 23h amask interrupt mask for alarm 24h loopb loopback register 25h txg transmit preamp. gain 26h rxg-1,0 receive preamp. gain (ch1 ch0) 27h rxg-3,2 receive preamp. gain (ch3 ch2) 31h srid silicon revision identification code STLC5046 10/27
registers description configuration register (conf) addr=00h; reset value=3fh bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 res lin amu sta pd3 pd2 pd1 pd0 res=0normal operation res=1 device reset: i/0n and csn are all inputs, dx is h.i. (equivalent to hw. reset). lin=0 a or m law pcm encoding lin=1 linear encoding (16 bits), two's comple- ment. amu=0 m law selection amu=1 a law selection (even bits inverted) sta=0 cs0 to cs3 scan the four slics con- nected to the i/o control port, each cs has a 31.25 m s repetition time. sta=1; i/o are static, cs0 to cs3 are config- ured as generic static i/o pd3..0=0 codec 3..0 is active pd3..0=1 codec 3..0 is in power down. when one codec is in power down the corresponding vfro output is forced to agnd. and the corre- sponding transmit time slot on dx is set in h.i. pin strap value: res 0 amu 0 pd3 pd2 pd1 pd0 i/o direction register (dir) addr=01h; reset value=00h addr=02h; reset value=x0h bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 io 7 io 6 io 5 io 4 io 3 io 2 io 1 io 0 io 11 io 10 io 9 io 8 io 11..0 = 0; i/o pin 11..0 is an input, data on the i/o input is written in datan register bit 11..0. io 11 ..0 = 1; i/o pin 11..0 is an output, data con- tained in datan register bit11..0 is transferred to the i/o output. pin strap value: 00000000 00000000 i/o data register channel #0 (data0) addr=03h; reset value=00h addr=04h; reset value=x0h if bit 4 of conf register (sta)=0 dynamic i/o mode: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 d0 7 d0 6 d0 5 d0 4 d0 3 d0 2 d0 1 d0 0 d0 11 d0 10 d0 9 d0 8 when cs0 is active d0 11..0 are transferred to the corresponding i/o pins configured as outputs (see dir register). for the i/o pins configured as inputs the corresponding d0 11..0 will be written by the values applied to those pins while cs0 is low. if bit 4 of conf register (sta)=1 static i/o mode: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ds 7 ds 6 ds 5 ds 4 ds 3 ds 2 ds 1 ds 0 ds 11 ds 10 ds 9 ds 8 d 11..0 are transferred to the corresponding i/o pins configured as outputs (see dir register). for the i/o pins configured as inputs the correspond- ing d 11..0 will be written by the values applied to those pins. pin strap value: 00000000 0000 i/o data register channel #1 (data1) addr=05h; reset value=00h addr=06h; reset value=x0h if bit 4 of conf register (sta)=0 dynamic i/o mode: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 d1 7 d1 6 d1 5 d1 4 d1 3 d1 2 d1 1 d1 0 d1 11 d1 10 d1 9 d1 8 when cs1 is active d 11..0 are transferred to the corresponding i/o pins configured as outputs (see dir register). for the i/o pins configured as inputs the corresponding d 11..0 will be written by the values applied to those pins while cs1 is low. if bit 4 of conf register (sta)=1 STLC5046 11/27
static i/o mode: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 cio 3 cio 2 cio 1 cio 0 cio0..3=0 the cs0..3 is a static input, data is written in data2 register bits 0..3. cio0..3=1 the cs0..3 is a static output, data is taken from data2 register bits 0..3. pin strap value: 00000000 0000 i/o data register channel #2 (data2) addr=07h; reset value=00h addr=08h; reset value=x0h if bit 4 of conf register (sta)=0 dynamic i/o mode: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 d2 7 d2 6 d2 5 d2 4 d2 3 d2 2 d2 1 d2 0 d2 11 d2 10 d2 9 d2 8 when cs2 is active d2 11..0 are transferred to the corresponding i/o pins configured as outputs (see dir register). for the i/o pins configured as inputs the corresponding d11..0 will be written by the values applied to those pins while cs2 is low. if bit 4 of conf register (sta)=1 static i/o mode: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 cd 3 cd 2 cd 1 cd 0 cd 3..0 are transferred to the corresponding cs pin if configured as static output (see register data1). for the cs pins configured as static in- puts the corresponding cd 3..0 will be written by the values applied to those pins. pin strap value: 00000000 0000 i/o data register channel #3 (data3) addr=09h; reset value=00h addr=0ah; reset value=x0h used only if bit 4 of conf register (sta)=0; dy- namic i/o mode: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 d3 7 d3 6 d3 5 d3 4 d3 3 d3 2 d3 1 d3 0 d3 11 d310 d39 d38 when cs3 is active d11..0 are transferred to the corresponding i/o pins configured as outputs (see dir register). for the i/o pins configured as inputs the corresponding d11..0 will be written by the values applied to those pins while cs3 is low. if bit4 of conf register (sta)=1 static i/o mode: can be used as general purpose r/w registers, without any direct action on the control of the de- vice. pin strap value: 00000000 0000 transmit gain channel #0 (gtx0) addr=0bh; reset value=00h bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00h:stop any trasmit signal, null level is transmit- ted in the corresponding timeslot on dx output. >00h:digital gain is inserted in the tx path equal to: 20log[0.25+0.75*(progr.value/256)] pin strap values: gx0=1: 0db gain (value = ffh): 11111111 gx0=0: -3.5db gain (value = 8fh): 10001111 transmit gain channel #1 (gtx1) addr=0ch; reset value=00h bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00h:stop any trasmit signal, null level is transmit- STLC5046 12/27
ted in the corresponding timeslot on dx output. >00h:digitalgain is inserted in the tx path equalto: 20log[0.25+0.75*(progr.value/256)] pin strap values: gx0=1: 0db gain (value = ffh): 11111111 gx0=0: -3.5db gain (value = 8fh): 10001111 transmit gain channel #2 (gtx2) addr=0dh; reset value=00h bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00h: stop any trasmit signal, null level is transmit- ted in the corresponding timeslot on dx output. >00h:digitalgain is inserted in the tx path equalto: 20log[0.25+0.75*(progr.value/256)] pin strap values: gx0=1: 0db gain (value = ffh): 11111111 gx0=0: -3.5db gain (value = 8fh): 10001111 transmit gain channel #3 (gtx3) addr=0eh; reset value=00h bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00h:stop any trasmit signal, null level is transmit- ted in the corresponding timeslot on dx output. >00h:digitalgain is inserted in the tx path equalto: 20log[0.25+0.75*(progr.value/256)] pin strap values: gx0=1: 0db gan (value = ffh): 11111111 gx0=0: -3.5db gain (value = 8fh): 10001111 receive gain channel #0 (grx0) addr=0fh; reset value=00h bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00h:stop any received signal, agnd level is forced on the vfro0 analog output. >00h:digitalgain is inserted in the rx path equalto: 20log[0.25+0.75*(progr.value/256)] pin strap values: gr0=1: -0.8db gain (value = e2h): 11100010 gr0=0: -2.36db gain (value = afh): 10101111 overall gain including also rxg: gr0 = 1:-0.8db; gr0 = 0: -4.3db receive gain channel #1 (grx1) addr=10h; reset value=00h bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00h:stop any received signal, agnd level is forced on the vfro1 analog output. >00h:digitalgain is inserted in the rx path equalto: 20log[0.25+0.75*(progr.value/256)] pin strap values: gr1=1: -0.8db gain (value = e2h): 11100010 gr1=0: -2.36db gain (value = afh): 10101111 overall gain including also rxg: gr1= 1:-0.8db; gr1 = 0: -4.3db receive gain channel #2 (grx2) addr=11h; reset value=00h bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00h:stop any received signal, agnd level is forced on the vfro2 analog output. >00h:digitalgain is inserted in the rx path equalto: STLC5046 13/27
20log[0.25+0.75*(progr.value/256)] pin strap values: gr2=1: -0.8db gain (value = e2h): 11100010 gr2=0: -2.36db gain (value = afh): 10101111 overall gain including also rxg: gr2 = 1:-0.8db; gr2 = 0: -4.3db receive gain channel #3 (grx3) addr=12h; reset value=00h bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00h:stop any received signal, agnd level is forced on the vfro3 analog output. >00h:digitalgain is inserted in the tx path equalto: 20log[0.25+0.75*(progr.value/256)] pin strap values: gr3=1: -0.8db gain (value = e2h): 11100010 gx3=0: -4.3db gain (value = afh): 10101111 overall gain including also rxg: gr3 = 1:-0.8db; gr3 = 0: -4.3db transmit time slot channel #0 (dxa0) addr=13h; reset value=00h bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 en0 t06 t05 t04 t03 t02 t01 t00 en0=0: selected transmit time slot on dx output is in h.i. en0=1: selected transmit time slot on dx output is active carrying out the pcm encoded signal of vfxi0. t06..0: define time slot number (0 to 127) on which pcm encoded signal of vfxi0 is carried out. if linear mode is selected (lin=1 of conf regis- ter) the 16 bits will be carried out as follows: the 8 most significative bits in the programmed time slot, the 8 least significative bits in the following timeslot. example: if t06..t00=00: ts0 ts1 1514131211109876543210 pin strap value (value 80h): 10000000 referred to fs0. transmit time slot channel#1 (dxa1) addr=14h; reset value=00h bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 en1 t16 t15 t14 t13 t12 t11 t10 en1=0: selected transmit time slot on dx output is in h.i. en1=1: selected transmit time slot on dx output is active carrying out the pcm encoded signal of vfxi1. t16..0:define time slot number (0 to 127) on which pcm encoded signal of vfxi1 is carried out. if linear mode is selected (lin=1 of conf regis- ter) the 16 bits will be carried out as follows: the 8 most significative bits in the programmed time slot, the 8 least significative bits in the following timeslot. example: if t16..t10=00: ts0 ts1 1514131211109876543210 pin strap value (value=80h) 10000000 referred to fs1. transmit time slot channel #2 (dxa2) addr=15h; reset value=00h bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 en2 t26 t25 t24 t23 t22 t21 t20 en2=0: selected transmit time slot on dx output is in h.i. en2=1: selected transmit time slot on dx output is active carrying out the pcm encoded signal of vfxi2. t26..0:define time slot number (0 to 127) on which pcm encoded signal of vfxi2 is carried out. if linear mode is selected (lin=1 of conf regis- STLC5046 14/27
ter) the 16 bits will be carried out as follows: the 8 most significative bits in the programmed time slot, the 8 least significative bits in the following timeslot. example: if t26..t20=00: ts0 ts1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pin strap value (value=80h) 10000000 referred to fs2. transmit time slot channel #3 (dxa3) addr=16h; reset value=00h bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 en3 t36 t35 t34 t33 t32 t31 t30 en3=0: selected transmit time slot on dx output is in h.i. en3=1: selected transmit time slot on dx output is active carrying out the pcm encoded signal of vfxi3. t36..0:define time slot number (0 to 127) on which pcm encoded signal of vfxi3 is carried out. if linear mode is selected (lin=1 of conf regis- ter) the 16 bits will be carried out as follows: the 8 most significative bits in the programmed time slot, the 8 least significative bits in the following timeslot. example: if t36..t30=00: ts0 ts1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pin strap value (value=80h) 10000000 referred to fs3. receive time slot channel #0 (dra0) addr=17h; reset value=00h bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 en0 r06 r05 r04 r03 r02 r01 r00 en0=0: disable reception of selected time slot. en0=1: selected receive time slot on dr input is pcm decoded and tranferred to vfro0 output. r06..0:define receive time slot number (0 to 127) on carrying the pcm signal to be decoded and tranferred to vfro0 output.if linear mode is se- lected (lin=1 of conf register) the 16 bits will be used as linear code as follows: the 8most sig- nificative bits in the programmed time slot, the 8 least significative bits in the following timeslot. example: if r06..r00=00: ts0 ts1 1514131211109876543210 pin strap value (value 80h): 10000000 referred to fs0. receive time slot channel #1 (dra1) addr=18h; reset value=00h bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 en0 r16 r15 r14 r13 r12 r11 r10 en1=0: disable reception of selected time slot. en1=1: selected receive time slot on dr input is pcm decoded and tranferred to vfro1 output. r16..0:define receive time slot number (0 to 127) on carrying the pcm signal to be decoded and tranferred to vfro1 output.if linear mode is se- lected (lin=1 of conf register) the 16 bits will be used as linear code as follows: the 8most sig- nificative bits in the programmed time slot, the 8 least significative bits in the following timeslot. example: if r16..r10=00: ts0 ts1 1514131211109876543210 pin strap value (value=80h) 10000000 referred to fs1. receive time slot channel #2 (dra2) addr=19h; reset value=00h bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 en2 r26 r25 r24 r23 r22 r21 r20 en2=0: disable reception of selected time slot. en2=1: selected receive time slot on dr input is pcm decoded and tranferred to vfro1 output. r26..0:define receive time slot number (0 to 127) STLC5046 15/27
on carrying the pcm signal to be decoded and tranferred to vfro2 output.if linear mode is se- lected (lin=1 of conf register) the 16 bits will be used as linear code as follows: the 8most sig- nificative bits in the programmed time slot, the 8 least significative bits in the following timeslot. example: if r26..r20=00: ts0 ts1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pin strap value (value=80h) 10000000 referred to fs2. receive time slot channel #3 (dra3) addr=1ah; reset value=00h bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 en3 r36 r35 r34 r33 r32 r31 r30 en3=0: disable reception of selected time slot. en3=1: selected receive time slot on dr input is pcm decoded and tranferred to vfro1 output. r36..0:define receive time slot number (0 to 127) on carrying the pcm signal to be decoded and tranferred to vfro2 output.if linear mode is se- lected (lin=1 of conf register) the 16 bits will be used as linear code as follows: the 8most sig- nificative bits in the programmed time slot, the 8 least significative bits in the following timeslot. example: if r36..r30=00: ts0 ts1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pin strap value (value=80h) 10000000 referred to fs3. pcm shift register (pcmsh) addr=1bh; reset value=00h bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 xs2 xs1 xs0 rs2 rs1 rs0 xs2..0:effective start of the tx frame is the pro- grammed values of clock pulses (0 to 7) after the fs rising edge. rs2..0:effective start of the rx frame is the pro- grammed values of clock pulses (0 to 7) after the fs rising edge. pin strap value (value=00h): 00000000 interrupt mask register for i/o port (dmask) addr=1ch; reset value=ffh addr=1dh; reset value=xfh bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 md7 md6 md5 md4 md3 md2 md1 md0 md11 md10 md9 md8 md11..0=1: the corresponding i/o doesn't gen- erate interrupt. md11..0=0: the corresponding i/o (programmed as input) generate interrupt if a change of status is detected. input lines with persistency check generate inter- rupt if the changed status remains stable longer than the time programmed in the persistency check registers pchka/b. lines without persis- tance check generate an immediate interrupt re- quest. mask register has no effect on those pins config- ured as outputs, those pins will not generate in- terrupt. pin strap value. 11111111 1111 interrupt mask register for cd port (cmask) addr=1eh; reset value=xfh bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 mc3 mc2 mc1 mc0 in mcu mode, dynamic i/o configuration, mcn bits are the disable/enable interrupt related to the channel n : mc3..0= 0 any i/o line of the related channel is enabled to generate interrupt depending on dmask setting. mc3..0=1 any i/o line of the related chanel is disabled to generate interrupt indipendently of dmask setting. in mcu mode, static i/o configuration, mcn bits are the interrupt mask bits related to csn that are configured as i/o lines. mc3..0=1: the corresponding i/o doesn't gener- ate interrupt. mc3..0=0: the corresponding i/o generate inter- rupt if a change of status is detected. STLC5046 16/27
input lines with persistency check generate inter- rupt if the changed status remains stable longer than the time programmend in the persistency check registers pchka/b lines without persistency check generate an im- mediate interrupt request. mask register has no effect on those pins config- ured as outputs, those pins will not generate in- terrupt. pin strap value (value=00h): 11111111 persistency check register (pchk-a/b) two input signals per channel , labeled a and b, are submitted to persistency check. in dynamic mode (sta=0), a and b inputs of the four channels, are sampled on the multiplexed lines io0 (pin13) and io1 (pin14). in static mode (sta=1) the persistency check is performed on four pairs of lines, assigned to each channel according to the table: chan# input a input b 0 io0 (pin 13) io1 (pin 14) 1 io4 (pin 17) io5 (pin 18) 2 io6 (pin 48) io7 (pin 47) 3 io10 (pin 44) io11 (pin 43) addr=1fh; reset value=00h addr=20h; reset value=00h bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ta7 ta6 ta5 ta4 ta3 ta2 ta1 ta0 tb7 tb6 tb5 tb4 tb3 tb2 tb1 tb0 ta7..0 and tb7..0, content of pchka and pchkb registers, define the minimum duration of input a and b to generate interrupt ; spurious transitions shorter than the programmed value are ignored. the time width can be calculated according to the formula: time-width a = (ta7..0) x 64 m s time-width b = (tb7..0) x 64 m s if pchka/b is programmed to 00h the persist- ency check is not performed and any detected transition will generate interrupt. all the inputs, with or without persistency check, are sampled with a repetition rate of 32 m s pin strap value: 00000000 00000000 interrupt register (int) addr=21h; reset value=00h bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ickf id3 id2 id1 id0 ickf = 1: if interrupt is generated by a change of bit 0 in register alarm. in dynamic i/o configuration the id3..0 bits latch the interrupt request from the related chan- nel. any single bit idn is cleared after reading related i/o register or by setting mcn bit high (i.e. when channel n is disabled to generate interrupt ). in static i/o configuration id0 and id2 bits latch the interrupt request from i/o11..0 and cs3..0 re- spectively: id0 : is set high when the interrupt is requested from any the i/o11..0 lines. id2: is set high when the interrupt is requested from any of the cs3..0 (configured as i/o). id0 and id2 are cleared after reading related i/o register. id1 and id3 are don't care. pin strap value (value=00b): 00000 alarm register (alarm) addr=22h; reset value=00h bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 por ckf ckf=1: if number of pcm clock pulses in one frame period does not match expected value. por=1: if a power on reset is detected during operation. the register alarm is cleared after reading op- eration only if signals are inactive. pin strap value (value=00h): 00 interrupt mask register for alarm (amask) addr=23h; reset value=11b bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 mcf STLC5046 17/27
mcf=1: the corresponding alarm bit (ckf) doesn't generate interrupt. mcf=0: the corresponding alarm bit (ckf) gen- erates interrupt. pin strap value (value=00h): 1 loopback register (loopb) addr=24h; reset value=00h bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 dl3 dl2 dl1 dl0 al3 al2 al1 al0 dl3..0=0: normal operation dl3..0=1: codec #3..0 is set in digital loopback mode, this means that the receive pcm signal applied to the programmed receive time slot is transferred to the programmed transmit time slot. al3..0=0: normal operation al3..0=1: codec #3..0 is set in analog loopback mode, this means that the vfro signal is tranferred to the vfxi input internally into the codec. when loopbacks are enabled the signal appears also at the corresponding vfro output. it is pos- sible to have no signal on the vfro output pro- gramming the gr register to 00h in case of digital loopback. pin strap value (value=00h): 00000000 transmit preamplifier gain register (txg) addr=25h; reset value=x0h bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 xg3 xg2 xg1 xg0 xg3..0=0:transmit preamplifier gain ch. 3..0 = 0db xg3..0=1:transmit preamplifier gain ch. 3..0 = 3.52db overall transmit gain depends on combination of txg and gtxn registers. for xgn=0 and gtxn=ff 0dbm0 at dx output correspond to - 15dbm| 600 w (137mvrms) at vfxi input. pin strap value (value=00h): 0000 receive amplifier gain registers (rxg-10/32) addr: 26h; reset value=00h addr: 27h; reset value=00h bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r12 r11 r10 r02 r01 r00 r32 r31 r30 r22 r21 r20 rn2 rn1 rn0 receive amplifier gain ch#n (db) 000 mute 0 0 1 -13.98 0 1 0 -7.96 0 1 1 -4.44 1 0 0 -1.94 101 0 110 0 111 0 overall receive gain depends on the receive am- plifier gain (rn2..0 setting in rxg reg.) and digital gain (grxn reg. setting). as a reference : when rn2..0 is set for 0db gain and grxn=ffh (max. gain) 0dbm0 at dr input correspond to a level at vfro output equal to 547mvrms (e.g. -3dbm 600ohm) pin strap value : rn2 rn1 rn0 grn = 1 1 1 1 grn = 0 1 0 0 overall gain including also grxn; grn = 1: -0.8db; grn = 0: -4.3db. silicon revision identification code (sr=d) addr: 31h; read only. xxxx0 0 0 0 STLC5046 18/27
zac rs zb mode za zb cc ch rs rac 20 19 41 17 rx iltf rdc cac cac 26 25 14 12 61 60 59 58 57 28 33 35 19 20 21 22 23 24 62 29 53 53 39 38 42 43 48 46 24 4 5 d2 43 det 44 gdk/al 3 d0 6 7 1 2 r0 r1 csin csout vreg base vbat ring rt1 39 r p1 r s1 r s2 tip pcd 38 40 rdc v bat v bat v bat tip vrel rr vring r p1 rt ring r p2 r p2 36 35 16 27 34 rt2 d99tl430 stlc3080 qext lcp 1511 28 crt d1 8 30 23 42 11 res rth ttxin ckring crt rth rlim tx 22 21 8 9 41 10 11 14 13 12 27 54 3 4 7 5 6 zac1 STLC5046 io0 io1 io2 io3 io4 io5 io6 io7 io8 cs1 cs2 io9 io10 io11 cs0 cs3 0.1 m f gnd v cc v cc (3.3v) v cc dx pcm interface dr fs mclk tsx m1 cap cap 0.1 m f m0 int cs cclk co 40 ci vfxi0 serial control ports to other slics vfro0 ctx 100nf crx to other slics v dd (3.3v) v cc (5v) bgnd rel0 rel1 relr v dd v cc agnd v cc v ee v dd v dd v ss sub vfro1 vfro2 vfro3 vfxi1 vfxi2 vfxi3 0.1 m f 31 rlim ref 32 iref 33 13 37 29 10 9 crev crev csrv cvb csrv 18 grx=+6db gtx=-12db agnd and bgnd must be shorted together on the line card figure 5. typical application circuit with stlc3080 without metering pulse injection and i/o pins in dynamic mode. STLC5046 19/27
electrical characteristics (typical value 25 c and nominal supply voltage. minimum and maximum value are guaranteed over the tem- perature 0 to 70 c range by production testing and supply voltage range shown in the operating ranges. per- formances over -40 to +85 c are guaranteedby product characterisation unless otherwise specified.) digital interface symbol parameter test condition min. typ. max. unit vil input voltage low di pins 0 0.2v dd v vih input voltage high di pins (1) 0.8v dd 5.5 v iil input current low di pins -10 10 m a iih input current high di pins -10 10 m a ci input capacitance (all dig. inp.) 5 pf vol output voltage low dx, tsx pins iol = 3.2ma (other pins iol = 1ma) 0 0.4 v voh output voltage high dx pinn ioh = -3.2ma (other pins iol = 1ma) 0.85v dd vdd v analog interface rix transmit input amplifier input impedance (vfxi) 1000 m w ror receive output impedance (-1.0v < vfro < 1.0v, ivfro = 1ma 1 w power dissipation idd (pd) power down current 9 11 ma idd active current 48 60 ma master clock timing f mclk frequency of mclk frequency is automatically detected 1.536 1.544 2.048 4.096 8.192 mhz mhz mhz mhz mhz t wmh period of mclk high measured from v ih to v ih 40 ns t wml period of mclk low measured from v il to v il 40 ns t rm rise time of mclk measured from v il to v ih 15 ns t fm fall time of mclk measured from v ih to v il 15 ns pcm interface timing t hmf hold time mclk low to fs low 10 ns t sfm setup time, fs high to mclk low 10 ns t dmd delay time, mclk high to data valid 10 ns t dmz (2) delay time, mclk low to dx disabled pull up resistor = 1k w c load = 30pf 540ns t sdm setup time, d r valid to mclk low 15 ns t hmd hold time, mclk low to d r invalid 5ns t dzc (2) delay time, mclk low to tsx high pull up resistor = 1k w c load = 30pf 40 ns t xdp delay time, mclk high to tsx low 10 ns (1) all the digital input are five-volt tollerant - maximum dc voltage 5.5v - maximum peak voltage 6.5v (2) it is defined as the time at which the output achivies the off state. STLC5046 20/27
12345671617 t hmf mclk t rm t fm t wmh t wml t sfm t wfh 1234567 16 t dmd t xdp fs tsx dx t dmz t dzc 1234567 16 t sdm t hmd dr d98tl386c figure 6a. pin-strap mode short frame sync. timing. 12345671617 t hmf mclk t rm t fm t wmh t wml t sfm t wfh 1234567 16 t dmd fs dx t dmz 1234567 16 t sdm t hmd dr d98tl387c t xdp tsx t dzc figure 6b. pin strap mode long frame sync. timing. note: t wfh has to be shorter than or equal to 3 mclk period to select short frame. note: t wfh has to be longer than 3 mclk period to select long frame. STLC5046 21/27
12345671617 t hmf mclk t rm t fm t wmh t wml t sfm 1234567 16 t dmd fs dx t dmz 1234567 16 t sdm t hmd dr d98tl388c t xdp tsx t dzc figure 6c. mcu mode frame sync. timing. electrical characteristics (continued) serial control port timing symbol parameter test condition min. typ. max. unit f cclk frequency of cclk 4.096 mhz t wch period of cclk high measured from v ih to v ih 100 ns t wcl period of cclk low measured from v il to v il 100 ns t rc rise time of cclk measured from v il to v ih 20 ns t fc fall time of cclk measured from v ih to v il 20 ns t hcs hold time, cclk high to cs low 5 ns t ssc setup time, cs low to cclk high 10 ns t sdc setup time, ci valid to cclk high 20 10 ns t hcd hold time, cclk high to ci invalid 10 ns t dcd delay time, cclk low to co data valid 30 ns t dsd delay time, cslow to co data valid 20 ns t ddz (1) delay time cshigh or 8th cclk low to co high impedance whichever comes first pull up resistor = 1k w c load = 30pf 50 ns t hsc hold time, 8th cclk high to cs high 10 ns t scs set up time, cs high to cclk high 10 ns (1) it is defined as the time at which the output achivies the off state. STLC5046 22/27
electrical characteristics (continued) slic control interface timing symbol parameter test condition min. typ. max. unit tcs chip select repetition rate 31.25 m s tcsw chip select pulse width 3.90 m s t div time cs low to data input valid 1.65 m s t dii time data input invalid to cs high 1.65 m s t doa time data output available to cs low 1.8 m s t don time cs high to data output not available 1.8 m s 123 byte 1 byte 2 45678 2345678 1 6543210 7 t rc t ssc t hcs t hcs t scs t scs t dsd t dcd t hcs t hcd t e t sdc cclk cs- co ci t fc t wch t wcl t hsc t ddz 76543210 d99tl454 figure 7. serial control port timing. t doa t don 31.25 m s (32khz) t div cs1 cs2 cs3 cs4 io (out) io (in) out ch0 in ch0 out ch1 in ch1 out ch2 in ch2 out ch3 in ch3 out ch0 d99tl460 in ch0 out ch1 in ch1 t dii figure 8. slic control port timing. STLC5046 23/27
transmission characteristics transmission transfer characteristics symbol parameter test condition min. typ. max. unit absolute levels (see table 19) the nominal 0dbm0 levels are: txg = 0db, gtxn = 0db (ff) 137 mvrms gxa transmit gain absolute accuracy -0.15 0.15 db gxag transmit gain variation with programmed gain (within 3db from max. dig. level) -0.2 +0.2 db gfx gain variation with frequency (relative to gain at 1004hz); 0dbm0 input signal 50hz 60hz 200hz 300-3000hz 3400hz 4000hz 4600hz and above -1.8 -0.15 -0.7 -20 -20 0 0.15 0 -14.0 -32.0 db gaxt gain variation with temperature -0.10 0.10 db gaxe gain variation with supplies 5% 0dbm0 input signal -0.05 0.05 db gtx gain tracking with tone (1004hz m law, 820hz alaw) gsx = 3 to -40dbm0 gsx = -40 to -50dbm0 gsx = -50 to -55dbm0 -0.2 -0.4 -1.2 0.2 0.4 1.2 db qdx quantization distortion with tone (1004hz m law, 820hz alaw) vfxi = +3dbm0 vfxi = 0 to -30dbm0 vfxi = -40dbm0 vfxi = -45dbm0 33 36 30 25 db nct transmit noise c message weighted ( m law) 12 dbrnco npt transmit noise psophometric weighted (a law) -68 dbm0p ddx (1) differential envelope delay (1 to 2.56khz input sinewave @ 0dbm0) 500hz 604hz 1000hz 1792hz 2604hz 2792hz 170 110 25 0 70 95 m s dax (1) absolute delay @ 1khz 500 to 2800hz 420 m s dpxm single frequency distortion (mu law 0dbm0 sinewave @ 1004hz) -46 db dpxa single frequency distortion (a law 0dbm0 sinewave @ 820hz) -46 db receive transfer characteristics absolute levels the nominal 0dbm) levels are vfro: rgx = 0db, grxn = 0db (ff) 547 mvrms gra transmit gain absolute accuracy (within 3db from max. dig. level) -0.15 0.15 db (1) typical value not tested in production. STLC5046 24/27
symbol parameter test condition min. typ. max. unit grag receive gain variation with programmed gain -0.2 +0.2 db gfr gain variation with frequency (relative to gain at 1004hz); 0dbm0 input signal. below 200hz 200hz 300-3000hz 3400hz 4000hz -0.25 -0.15 -0.7 0.15 0.15 0.15 0 -14 db gart gain variation with temperature -0.1 +0.1 db gare gain variation with supplies 0dbm0 input signal v cc =v dd = 3.3v 5% -0.05 0.05 db gtr gain tracking with tone (1004hz mu law, 820hz a law) dr = 3 to -40dbm0 dr = -40 to -50dbm0 dr = -50 to -55dbm0 -0.2 -0.4 -1.2 0.2 0.4 1.2 db qdr quantization distortion with tone (1004hz mu law, 820hz a law) dr = 3 dbm0 dr = 0 to -30dbm0 dr = -40dbm0 dr = -50 to -55dbm0 33 36 30 25 db gspr out of band spourious noise 0dbm0 180 to 3400hz sinewave at dr 32 db ncr receive noise c message weighted ( m law) 8 11 dbrnco npr receive noise psophometric weighted (a law) -82 -79 dbm0p ddr (1) differential envelope delay (1 to 2.56khz input sinewave @ 0dbm0) 500hz 604hz 1000hz 1792hz 2604hz 2792hz 25 0 0 0 90 115 m s dar (1) absolute delay @ 1khz 500 to 2800hz 440 m s dpr1 single frequency distortion (0dbm0 sinewave @ 1004hz) -46 db psrr power supply rejection ratio 1khz, 50mvrms 30 db ctx-r transmit to receive crosstalk (input signal 200hz to 3450hz at 0dbm0) -76 db ctr-x receive to transmit crosstalk (input signal 200hz to 3450hz at 0dbm0) -76 db ct-ich inter channel crosstalk, tx and tx direction. input 200 to 3450hz at 0dbm0 at vfxi of one channel; all other vfxi inputs and all dr inputs receive idle signal. output is measured at dx of the 3 idle channels. input 200 to 3450hz at 0dbm0 at dr of one channel; all other dr inputs and all vfxi inputs receive idle signal. output is measured at vfro of the 3 idle channels. -78 db transmission characteristics receive transfer characteristics (continued) (1) typical value not tested in production. STLC5046 25/27
tqfp64 dim. mm inch min. typ. max. min. typ. max. a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.18 0.23 0.28 0.007 0.009 0.011 c 0.12 0.16 0.20 0.0047 0.0063 0.0079 d 12.00 0.472 d1 10.00 0.394 d3 7.50 0.295 e 0.50 0.0197 e 12.00 0.472 e1 10.00 0.394 e3 7.50 0.295 l 0.40 0.60 0.75 0.0157 0.0236 0.0295 l1 1.00 0.0393 k 0 (min.), 7 (max.) a a2 a1 b c 16 17 32 33 48 49 64 e3 d3 e1 e d1 d e 1 k b tqfp64 l l1 seating plane 0.10mm outline and mechanical data STLC5046 26/27
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specification mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. the st logo is a registered trademark of stmicroelectronics ? 2000 stmicroelectronics printed in italy all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com STLC5046 27/27

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